This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-045597, filed Feb. 22, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device using a MIS field effect transistor.
2. Description of the Related Art
Silicon MOS field effect transistors (MOSFETs) as the mainstream of current semiconductor devices have simultaneously achieved micropatterning of elements, particularly high-density integration and larger driving force by reduction in gate length. However, it has been pointed out that element micropatterning complying with the conventional trend will reach physical and economical limits sooner or later. A technique for higher speeds and smaller power consumption by a method other than micropatterning must be established.
It has been known that the electron and hole mobilities increase in a Si crystal to which stress strain is applied. High-performance devices in which this characteristic is applied to the channel of a MIS (Metal Insulator Semiconductor) field effect transistor (MISFET) have been manufactured as prototypes.
More specifically, a MISFET using a semiconductor substrate in which a SiGe crystal layer slightly larger in lattice constant than the Si crystal is used as an underlayer and a Si thin layer is stacked on the SiGe crystal layer to form a strained Si layer has been proposed. In the MISFET, the carrier exhibits high mobility in the strained Si layer. By using the strained Si layer as a channel region, a high speed and small power consumption can be realized.
On the other hand, a high channel impurity concentration for suppressing the short channel effect of the MISFET increases the parasitic capacitance of the source/drain diffusion layer. It is known that the parasitic capacitance can be effectively reduced by using, for example, a semiconductor substrate having an SOI (Silicon On Insulator) structure in which an insulating layer is formed on a silicon wafer and a semiconductor layer is formed on the insulating layer.
From this, a MISFET using a semiconductor substrate in which a silicon wafer/SiGe crystal layer/Si oxide layer (insulating layer)/SiGe crystal layer/strained Si layer are formed has been proposed.
However, this structure suffers many defects on the interface between the insulating layer and the SiGe crystal layer, posing the following problem. That is, this structure is inferior in interface characteristic to an interface between the Ge-free Si layer and insulating layer of a general SOI substrate. Further, this structure has a larger leakage current than that in a MISFET using an unstrained Si layer of the SOI as a channel.
Demands have, therefore, arisen for the implementation of a semiconductor device having a MISFET improved such that defects on the interface between the insulating layer and the SiGe crystal layer and the like do not adversely affect the leakage current characteristic and the like in a MISFET using the strained Si layer as a channel layer.
A semiconductor device according to a first aspect of the invention comprises
an insulating layer having a major surface;
a semiconductor board formed on a selected portion of the major surface of the insulating layer, the semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other, and substantially perpendicular to the major surface of the insulating layer, and an upper surface opposed to the bottom surface;
a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, the semiconductor layer having a lattice constant different from that of the semiconductor board, and having source and drain regions spaced apart from each other and a channel region between the source and drain regions, a channel length direction of the channel region being substantially parallel to the major surface of the insulating layer, and an area at a surface of the channel region being larger than an area of the bottom surface of the semiconductor board;
a gate insulating layer formed on the channel region of the semiconductor layer; and
a gate electrode formed on the gate insulating layer.
A semiconductor device according to a second aspect of the invention comprises
an insulating layer having a major surface;
a p-type semiconductor board formed on a first selected portion of the major surface of the insulating layer, the p-type semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other, and substantially perpendicular to the major surface of the insulating layer, and an upper surface opposed to the bottom surface of the p-type semiconductor board;
a first semiconductor layer formed on at least one of the major side surfaces of the p-type semiconductor board, the first semiconductor layer having a lattice constant different from that of the p-type semiconductor board and having n-type source and drain regions spaced apart from each other and a first channel region provided in a p-type region between the n-type source and drain regions, a channel length direction of the first channel region being substantially parallel to the major surface of the insulating layer, and an area at a surface of the first channel region being larger than an area of the bottom surface of the p-type semiconductor board;
a first gate insulating layer formed on the first channel region of the first semiconductor layer;
a first gate electrode formed on the first gate insulating layer;
an n-type semiconductor board formed on a second selected portion of the major surface of the insulating layer, the n-type semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other, and substantially perpendicular to the major surface of the insulating layer, and an upper surface opposed to the bottom surface of the n-type semiconductor board;
a second semiconductor layer formed on at least one of the major side surfaces of the n-type semiconductor board, the second semiconductor layer having a lattice constant different from that of the n-type semiconductor board and having p-type source and drain regions spaced apart from each other and a second channel region provided in an n-type region between the p-type source and drain regions, a channel length direction of the second channel region being substantially parallel to the major surface of the insulating layer, and an area at a surface of the second channel region being larger than an area of the bottom surface of the n-type semiconductor board;
a second gate insulating layer formed on the second channel region of the second semiconductor layer; and
a second gate electrode formed on the second gate insulating layer.
A semiconductor substrate manufacturing method suitable for forming a CMIS semiconductor device comprises
forming a mask having a silicon oxide layer and a silicon nitride layer stacked on the silicon oxide layer selectively formed on a silicon layer of a semiconductor substrate, the semiconductor substrate having an insulating layer and the silicon layer stacked on the insulating layer,
stacking a SiGe layer on the silicon layer except a portion where the mask is formed,
performing thermal oxidization processing for the semiconductor substrate to form an oxide layer on a surface of the SiGe layer and at the same time change a multilayered structure of the SiGe layer and the silicon layer into a single SiGe layer, and
removing the oxide layer and the mask.
A semiconductor device according to a third aspect of the present invention comprises
an insulating layer having a major surface;
a first semiconductor board formed on a first selected portion of the major surface of the insulating layer, the first semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other and substantially perpendicular to the major surface of the first insulating layers, and an upper surface opposed to the bottom surface of the first semiconductor board;
a first semiconductor layer formed on at least one of the major side surfaces of the first semiconductor board, the first semiconductor layer having a lattice constant different from that of the first semiconductor board, and having a first source region and a first drain region spaced apart from each other and a first channel region provided between the first source region and the first drain region, a channel length direction of the first channel region being substantially parallel to the major surface of the insulating layer, and an area at a surface of the first channel region being larger than an area of the bottom surface of the first semiconductor board;
a first gate insulating layer formed on the first channel region of the first semiconductor layer;
a first gate electrode formed on the first gate insulating layer;
a second semiconductor board formed on a second selected portion of the major surface of the insulating layer, the second semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other and substantially perpendicular to the major surface of the second insulating layers, and an upper surface opposed to the bottom surface of the second semiconductor board;
a second semiconductor layer formed on at least one of the major side surfaces of the second semiconductor board, the second semiconductor layer having a lattice constant different from that of the second semiconductor board, and having a second source region and a second drain region spaced apart from each other and a second channel region provided between the second source region and the second drain region, a channel length direction of the second channel region being substantially parallel to the major surface of the insulating layer, and an area at a surface of the second channel region being larger than an area of the bottom surface of the second semiconductor board;
a second gate insulating layer formed on the second channel region of the second semiconductor layer;
a second gate electrode formed on the second gate insulating layer.